1. Field of Use
The present invention relates to devices utilizing bipolar and field effect transistors (FETs). More particularly, the present invention relates to BiCMOS buffers, inverters, and gates which utilize differential inputs and provide increased output drive at a buffered output.
2. Background Art
The new technology of BiCMOS which utilizes both bipolar and CMOS transistors in a single device has been increasingly explored in the past few years. The advantage of BiCMOS circuits over conventional CMOS or bipolar circuits is that the high speed characteristic of bipolar circuits can be obtained with an integration density and low power consumption characteristic of CMOS circuits.
Typical of BiCMOS buffers, inverters and gates known in the art are the following patents and disclosures: U.S. Pat. No. 4,558,234 to Suzuki et al.; U.S. Pat. No. 4,638,186 to McLaughlin; U.S. Pat. No. 4,649,294 to McLaughlin; U.S. Pat. No. 4,733,110 to Hara et al.; EPO Publication 0212004; IBM TDB Vol. 29, #3, August 1986, p.1191-1192; Japanese Patent Publication (JPP) 62-26691 to Miyaoka et al; JPP 62-230221 to Ueno; and JPP 61-274512 to Nakamura. Additional buffers, inverters and gates are disclosed in the following articles: Liang-Tsai Lin et al., "A 9100 Gate ECL/TTL Compatible BiCMOS Gate Array", IEEE 1987 Custom Integrated Circuits Conference: pp.190-194; P. Simon Bennett et al., "High Performance BIMOS Gate Arrays with Embedded Configurable Static Memory", IEEE 1987 Custom Integrated Circuits Conference: pp.195-197; Yoji Nishio et al., "0.45ns 7K Hi-BiCMOS Gate Array with Configurable 3-Port 4.6K SRAM", IEEE 1987 Custom Integrated Circuits Conference: pp.203-204; Chu et al., "A Comparison of CMOS circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Journal of Solid-State Circuits: Vol Sc- 22, No. 4 (Aug. 1987); Masaharu Kubo, et al., "Perspective on BiCMOS VLSI's", IEEE Journal of Solid-State Circuits: Vol. 23, No. 1 (Feb. 1988); Shih-Lien Lu, "Implementation of Iterative Networks with CMOS Differential Logic" IEEE Journal of Solid-State Circuits: Vol. 23, No. 4 (Aug. 1988).
Common to almost all of the above disclosures is that either a single input or non-differential multiple inputs are utilized as inputs into the circuits, or that a non-synchronous differential input is utilized. The non-synchronous differential input is typically provided via use of one or more inverters which slows the circuit and causes the differential input to have phase disparity.